1. Field of the Invention
This invention relates to integrated circuits and in particular to a structure for accurately cancelling electrical charge which is transferred to a circuit node by the switching "ON" or "OFF" of a field effect transistor whose drain or source is connected to that node and to the method of operating such a structure. More particularly, this invention makes possible a significant increase in the accuracy with which unwanted charge transferred by the application or removal of a gate voltage to a field effect transistor is cancelled.
2. Prior Art
In a transistor switch of the prior art (FIG. 1) incorporating an MOS transistor between an input terminal A and an output terminal B, the application of a gate voltage, such as voltage V.sub.g1, to the gate G1 of the transistor results in the transfer of charge within the semiconductor material in which the source, drain, and channel region are formed. To the extent this charge reaches the drain D1 of the MOS transistor and thus appears on the output terminal B, this charge represents noise or unwanted distortion in the signal on the output terminal B. To cancel this charge, a capacitor C1 was provided with one of its leads connected to the output terminal B and the other of its leads being connected to a voltage which was the complement of the gate voltage used to drive the MOS transistor. While this structure resulted in a portion of the unwanted charge being cancelled by an opposite charge on the capacitor, the design limitations on the structures were such that it was difficult to obtain precise charge cancellation. This problem was made more difficult by manufacturing tolerances and variations, and by the fact that the cancellation ideally should occur over the complete temperature range for which the transistor switch is designed to operate.
An attempt to solve this problem is illustrated in FIG. 2 where the capacitor C1 of FIG. 1 is replaced by another MOS transistor Q2 designed to match the transistor Q1. The drain of transistor Q2 is connected to terminal B of the circuit while the source of transistor Q2 is allowed to float. Application of a gate voltage V.sub.g1 to gate G1 of transistor Q1 occurred simultaneously with the application of a gate voltage V.sub.g2, complementary to V.sub.g1, to the gate G2 of the transistor Q2. The induced charge transferred to the drain D1 of transistor Q1 was then approximately cancelled by a charge of opposite polarity in the drain D2 of transistor Q2. However, difficulties arose with the circuit of FIG. 2 in that when transistor Q2 was in the OFF stage the source S2 of transistor Q2 gradually assumed the potential of the bulk semiconductor material because of leakage current flowing across the source-bulk junction. Accordingly, when the gate voltage V.sub.g2 was applied to transistor Q2, not only was a charge transferred to the drain D2 but additional charge had to be transferred to bring the source S2 back to the potential on the output terminal B. The accuracy with which the induced charge present in drain D1 was cancelled by the charge in drain D2 thus depended upon the time between application of the gate voltages V.sub.g1 and V.sub.g2 to the gates G1 and G2. Thus the accuracy of the circuit was dependent upon the time interval between switching events, the bulk bias voltage, and temperature (because the leakage current from source S2 to the bulk material was temperature dependent). To overcome this problem the prior art eliminated the source region from the charge cancelling transistor thereby leaving only the drain region D2 as in FIG. 3. However, even that structure gave imprecise cancelling due to an extra capacitance associated with the extension of the gate over the region of semiconductor material in which the source region would formerly have been formed.